`timescale 1ns / 1ns

module tb_brent_kung();
    wire  c_out;
    wire [31:0]  S;
    reg  c_in;
    reg [31:0]  B;
    reg [31:0]  A;
    reg [31:0] sum;

    reg result;
    integer i = 0;

    brent_kung DUT( S, c_out, A, B, c_in );

    initial begin
        A = 32'h0000_0000;
        B = 32'hffff_ffff;
        c_in = 1'b0;
        sum = A + B + c_in;
        result = |(sum & S);
        #10;
        A = 32'hffff_ffff;
        B = 32'h0000_0000;
        c_in = 1'b1;
        sum = A + B + c_in;
        result = |(sum & S);
        #10;
        A = 32'hffff_ffff;
        B = 32'h0000_0000;
        c_in = 1'b1;
        sum = A + B + c_in;
        result = |(sum & S);
        #10;
        A = 32'h0000_0000;
        B = 32'hffff_ffff;
        c_in = 1'b0;
        sum = A + B + c_in;
        result = |(sum & S);
        /*
        for (i = 0; i < 3; i = i + 1) begin
            c_in = 0;
            A = i;
            B = i;
            sum = A + B + c_in;
            result = |(sum & S);
            #10;
        end
        */
        #20;
    end
endmodule
